Graphics processing systems
US9767595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2013 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Dec 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.