Operation aware auto-feedback SRAM
US9767890B2 · kind B2 · utility
0Cited by
4References
17Claims
0Family size
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Inventors
Key dates
| Filing date | Dec 31, 2011 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Feb 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.