Passive SRAM write assist
US9767891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.