Mitigating electromigration effects using parallel pillars
US9768111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.