Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts
US9768190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Dec 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/00
Abstract
A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.