Bottom pinned SOT-MRAM bit structure and method of fabrication
US9768229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Oct 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.