Metal oxide TFT with improved source/drain contacts and reliability
US9768322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Aug 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.