Resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof
US9768381B2 · kind B2 · utility
1Cited by
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6Claims
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Key dates
| Filing date | Jul 13, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jul 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
Abstract
The present invention relates to a resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof. Especially, the present invention provides a technique forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate in order that an electric field is focused on the tip of the bottom electrode across a top electrode and that a region where conductive filaments are formed is maximally minimized or localized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.