Memory effect reduction using low impedance cascode biasing
US9768743B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jun 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2201/3209
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a reference voltage circuit, a filter circuit configured to receive an output of the reference voltage circuit, and a voltage follower configured to receive an output of the filter circuit and generate a bias voltage. The filter circuit is configured to combine signals on a reference ground with the output of the reference voltage circuit. A method of providing a bias voltage includes generating a reference voltage using a reference voltage circuit, filtering the reference voltage to generate a second voltage using a filter circuit, and generating the bias voltage according to the second voltage using a voltage follower circuit. Filtering the reference voltage includes combining a fluctuation of the reference ground with the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.