Failsafe interface circuit and related method
US9768768B2 · kind B2 · utility
3Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device includes a transistor cascode circuit including a first transistor configured to pull up voltage of a bulk and a node in response to a first control signal, and a second transistor configured to pull up voltage of an interface (I/O) pin in response to a second control signal. The device further includes a third transistor configured to pull down voltage of the I/O pin in response to a third control signal, and a feedback circuit configured to turn off the first transistor when the voltage of the I/O pin is above a predetermined level during a failsafe period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.