Method and system for implementing high-speed interfaces between semiconductor dies in optical communication systems
US9772460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2011 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4286
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.