Charging scan and charge sharing scan double output GOA circuit
US9773467B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2015 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Apr 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M−2th high frequency clock signals (CK(M), CK(M−2)), a stage transfer signal (ST(n−2)) generated by the n−2th stage GOA unit circuit, a charging scan signal (CG(n−2)) generated by the n−2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n−2)) generated by the n−2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.