Method for manufacturing semiconductor device
US9773707B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Aug 28, 2015 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0193
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.