Biasing scheme for high voltage circuits using low voltage devices
US9774324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2014 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Mar 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.