Circuit and method for generating clock-signals

US9774326B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Hua Tang · Shanghai, CN
• Fei Liu · Wuxi, CN
• Chia-Chi Yang · New Taipei, TW
• Benpeng Xun · Shanghai, CN
• Haifeng Yang · Shanghai, CN

Key dates

• Filing date: May 31, 2016
• Grant date: Sep 26, 2017
• Expiry date: May 31, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K5/1515
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.