Bridged imbalance PUF unit circuit and multi PUF circuits
US9774327B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2017 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Feb 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3278
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a bridge imbalance PUF unit circuit and multi PUF circuits; the bridge imbalance PUF unit circuit comprises a four-arm bridge unit circuit and a contrast output unit circuit; the multi PUF circuits comprise a timing controller, a row decoder, a column decoder, a memory array, a row output circuit and a column output circuit; each memory unit in the memory array comprises a bridge imbalance PUF unit circuit and 4 NMOS tubes; the present invention features in higher randomness that is up to 51.8% at the supply voltage of 1.2V under the temperature of 25° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.