Preventing timing violations
US9774329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2014 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Oct 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.