Statistical estimation-based noise reduction technique for low power successive approximation register analog-to-digital converters
US9774339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2016 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are systems and methods that describe statistical estimation based noise reduction for SAR ADCs. For SAR ADCs, the conversion error can be available at the comparator input. Although a noisy 1-bit comparator may not be able to produce an accurate estimation for its input if used only once, the comparison can be repeated multiple times for a designated bit of the multi-bit SAR ADC. This can allow for the improvement of the estimation accuracy by examining the probability of the comparator output being “1” or “0”. The estimation of a signal from a noisy environment using multiple trials can be cast as a classic statistical estimation issue. In one aspect of the disclosure, an optimal Bayes estimator is disclosed to achieve a low estimation error from the comparator on a designated bit of the multi-bit SAR ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.