Power failure detection system and method
US9778988B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Nov 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power failure monitoring system and a method are disclosed herein, where the power failure monitoring system includes a motherboard, a board, a complex programmable logic device (CPLD) and a baseboard management controller (BMC) module. The motherboard includes a central processing unit (CPU) power and a non-CPU power. The board includes a board power. The BMC module includes a register that is electrically coupled to the CPLD. The CPLD is configured to execute a shutdown process when power failure occurs, identify a power failure type, and determine whether to execute a restart process according to the power failure type. If the restart process is executed and a count of the restart process reaches a predetermined count, the CPLD records lock information in the register. The BMC module is configured to record the count of the restart process, and execute a lock process according to the lock information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.