Non-volatile memory controller cache architecture with support for separation of data streams

US9779021B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Charles J. Camp · Sugar Land, US
• Timothy J. Fisher · Cypress, US
• Aaron D. Fry · Richmond, US
• Nikolas Ioannou · Zürich, CH
• Ioannis Koltsidas
• Roman A. Pletka · Horgen, CH
• Sasa Tomic · Adliswil, CH
• Andrew D. Walls · San Jose, US

Key dates

• Filing date: Dec 19, 2014
• Grant date: Oct 3, 2017
• Expiry date: Apr 16, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/7208
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports separation of data streams, and the cache architecture supports parallel writes to different non-volatile memory channels. Additionally, the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes. Furthermore, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address. Other systems, methods, and computer program products are described in additional embodiments.