Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design
US9779201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2015 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Oct 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one general aspect, a method may include receiving a digital circuit model that includes models of a clock mesh and a plurality of logic circuits, each logic circuit associated with end-points of the logic circuit. The method may also include identifying a cluster of end-points, wherein the cluster is associated with a common version of the clock signal. The method may also include identifying an associated skew-schedule for each end-point. The method may include determining a timing slack and skew schedule for each end-point within the cluster. The method may include adjusting a clock-gater cell, based upon a common push/pull schedule associated with the cluster. The method may further include inserting, for at least one end-point of the cluster, a skew-buffer, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the end-point's skew schedule and the common push/pull schedule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.