Computer architecture using compute/storage tiles
US9779785B2 · kind B2 · utility
4Cited by
24References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 11, 2015 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jun 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory elements to be used as local memories (including content addressable memories or random access memories), logic elements or interconnect elements. The ability to dynamically change the function of any of these tiles allows tight integration of memory and logic tailored to particular calculation problems reducing costs in data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.