InP-based transistor fabrication
US9780190B2 · kind B2 · utility
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266References
20Claims
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Key dates
| Filing date | Oct 18, 2012 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.