Methods of reducing the electrical and thermal resistance of SiC substrates and devices made thereby
US9780206B2 · kind B2 · utility
4Cited by
0References
9Claims
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Key dates
| Filing date | Feb 29, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Feb 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.