Self-aligned high voltage LDMOS
US9780207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2015 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods for forming a device are disclosed. The method includes providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer. The surface substrate is defined with a device region. A transistor having a gate is formed in the device region. A first diffusion region is formed adjacent to a first side of the gate and a second diffusion region is formed adjacent to and displaced away from a second side of the gate. At least a first drift isolation region is formed in the surface substrate adjacent to and underlaps the second side of the gate. A drift well is formed in the surface substrate encompassing the first drift isolation region. A device isolation region surrounding the device region is formed in the surface substrate. The device isolation region includes a second depth which is deeper than a first depth of the first drift isolation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.