Power detector circuit using native transistor
US9780776B1 · kind B1 · utility
3Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Nov 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/16576
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic circuit includes a native N-channel Metal-Oxide-Semiconductor (NMOS) transistor and a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. The gates of the native NMOS transistor and the PMOS transistor and the source of the native NMOS transistor are grounded. The drains of the native NMOS transistor and the PMOS transistors are connected to one another and to an output port, and the source of the PMOS transistor is connected to an input voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.