Methods and apparatuses for offsetting aging in pass transistors
US9780793B2 · kind B2 · utility
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4References
20Claims
0Family size
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Key dates
| Filing date | Jan 6, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jan 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. By applying such a voltage for a brief period of time such as one second, the aging process is essentially nullified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.