Successive approximation register analog to digital converter with multiple split digital to analog convertors
US9780804B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital to analog convertor comprises an output line; first, second and third pluralities of capacitors; and first and second bridge capacitors. The first plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a first least significant bit capacitor of a first capacitance value. The second plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a second capacitor of the first capacitance value. The third plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a third capacitor of the first capacitance value. The first bridge capacitor bridges the output line between the first plurality of capacitors and the second plurality of capacitors. The second bridge capacitor bridges the output line between the second plurality of capacitors and the third plurality of capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.