Methods and devices for spur cancellation in digital phase locked loops
US9780945B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Apr 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Embodiments related to systems, methods, and computer-readable media to enable a digital phase locked loop are described. In one embodiment, a digital synthesizer comprises a digital phase locked loop with detection circuitry to calculate an estimate of a magnitude and a phase of a spurious response from an error signal within the digital phase locked loop. The digital phase locked loop further comprises generation circuitry to generate an inverse spur based on the estimate of the magnitude and the phase, and further comprises injection circuitry to inject the inverse spur into the digital phase locked loop. In some embodiments, least mean squares (LMS), recursive least squares (RLS), or other such adaptation is used to estimate the magnitude and phase of the spurious response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.