Analog equalizer
US9780979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2017 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jan 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03273
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.