Method, device, and system for processing PCIe link fault
US9785530B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 22, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Feb 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is disabled, wherein the link includes M lanes numbered in a first order. Based upon the determination, the first PCIe apparatus obtains a number N indicating a number of available lanes of the link by performing a lane negotiation with the second PCIe apparatus. Then, a processor determines that N<M/2. Based upon the determination, the first PCIe apparatus re-numbers at least some of the lanes of the link in a reverse order opposite to the first order as instructed by the processor. At last, the first PCIe apparatus continue to perform a negotiation with the second PCIe apparatus to obtain available lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.