Computer implemented system and method for modifying a layout of standard cells defining a circuit component
US9785740B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Dec 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented system and method is provided for modifying a layout of one or more standard cells defining a circuit component, the layout providing a layout pattern for a process technology. The method comprises receiving, after completion of one or more initial place and route operations, an input data file that includes the layout pattern of the layout. The layout includes the one or more standard cells and placement and routing information generated by the one or more initial place and route operations. The method further comprises identifying one or more metal portions associated with one or more rails of the one or more standard cells of the layout. A metal fill operation is then performed using the input data file in order to generate a modified input data file. The metal fill operation includes modifying the one or more metal portions with one or more metal fill patterns to form a reduced resistive path associated with the one or more metal portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.