Semiconductor memory devices, memory systems including the same and method of correcting errors in the same
US9786387B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Sep 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.