Method for reducing contact resistance
US9786555B1 · kind B1 · utility
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11Claims
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Key dates
| Filing date | Feb 13, 2017 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Feb 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for reducing contact resistance, including depositing a GST layer on an InGaAs substrate, generating an InGaAs/GST/Ni stacked structure by depositing a Ni layer on the GST layer, and thermally treating the stacked structure to rearrange components of the GST layer and to generate a Ni—InGaAs alloy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.