Transistor arrangement
US9786640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.