Non-volatile memory devices including charge storage layers
US9786675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Feb 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.