Semiconductor device and method of manufacturing the same
US9786735B2 · kind B2 · utility
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7Claims
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Key dates
| Filing date | Dec 14, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.