Method for forming semiconductor device structure
US9786754B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2017 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/2527
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device structure is provided. The method includes: forming a plurality of trenches in the substrate; forming a gate dielectric layer lining the trenches; filling the trenches with a gate material; etching back the gate material to expose an upper portion of the trenches; forming a first dielectric layer to refill the upper portion of the trenches, and to cover a substrate surface between the trenches; performing a first chemical mechanical planarization process to partially remove the first dielectric layer until the substrate surface between the trenches is exposed. The method also includes using the first dielectric layer in the upper portion of the trenches as an etching mask, etching the substrate through the exposed substrate surface to form a self-aligned contact opening between the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.