Semiconductor device having multiwork function gate patterns
US9786759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Feb 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.