Efficient coding with single-error correction and double-error detection capabilities
US9787329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Oct 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/617
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for data coding includes an encoder and a decoder. The encoder is configured to receive input data including one or more m-bit data groups that are associated with respective group indices, to generate a code word that includes the input data and an m-bit redundancy that depends on the data groups and on the respective group indices, and to send the code word over a channel. The decoder is connected to the channel and is configured to produce a syndrome that equals zero when the code word is error-free, and when the code word contains a single error caused by the channel, is indicative of an erroneous group in which the single error occurred, and of a location of the single error within the erroneous group, and to recover the input data by correcting the single error at the location in the erroneous group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.