Demodulation technique
US9787433B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2013 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jun 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03426
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique for assessing the reliability of bits received by a modulation symbol on a channel is provided. A providing circuit provides an input dataset including a plurality of input values. The input values correspond to different transmit hypotheses according to a modulation alphabet used for encoding the bits in the symbol. A computing circuit performs a first computing step and a second computing step. In the first computing step, a first intermediary dataset is computed by combining the input values of the input dataset according to a first combination scheme. In the second computing step, a second intermediary dataset is computed by combining the input values of the input dataset according to a second combination scheme. The second combination scheme is different from the first combination scheme. An assessing circuit assesses the reliability of the bits based on the first intermediary dataset and the second intermediary dataset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.