LVDS data recovery method and circuit
US9787468B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2014 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jul 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.