Packet processing in a parallel processing environment
US9787612B2 · kind B2 · utility
4Cited by
15References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/52
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Processing packets in a system that includes a plurality of interconnected processing cores is described. The processing includes receiving packets into one or more queues, associating at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate, mapping a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and at least one rate associated with a node not in the set, and processing the packets in the mapped processor cores according to the hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.