Layout and timing schemes for ping-pong readout architecture
US9787928B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Jan 6, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jan 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/76
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Ping-pong readout architecture allows for faster frame rates in CMOS image sensors. However, various problems are created by this architecture due to cross-talk between components. Provided herein are novel ping-pong readout layouts which better isolate components to reduce crosstalk issues. Also provided herein are novel timing schemes for operating ping-pong readout circuits which prevent crosstalk signal spikes or readout corruption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.