Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation
US9788011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2017 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jan 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.