Low power integrated analog mathematical engine
US9791638B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Mar 15, 2014 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Apr 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for creating on chip analog mathematical engines is provided utilizing a neural network with a switched capacitor structure to implement coefficients for weighted connections and error functions for the neural network. The neural networks are capable of any transfer function, learning, doing pattern recognition, clustering, control or many other functions. The switched capacitor charge controls allow for nodal control of charge transfer based switched capacitor circuits. The method reduces reliance on passive component programmable arrays to produce programmable switched capacitor circuit coefficients. The switched capacitor circuits are dynamically scaled without having to rely on switched in unit passives, such as unit capacitors, and the complexities of switching these capacitors into and out of circuit. The current, and thus the charge transferred is controlled at a nodal level, and the current rather than the capacitors are scaled providing a more accurate result in addition to saving silicon area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.