Patent · US Active

Reducing latency by persisting data relationships in relation to corresponding data in persistent memory

US9792224B2 · kind B2 · utility

5Cited by

31References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Karthik Kumar · Chandler, US
Martin P. Dimitrov · Chandler, US
Thomas Willhalm · Sandhausen, DE

Key dates

Filing date	Oct 23, 2015
Grant date	Oct 17, 2017
Priority date	—
Expiry date	Jan 14, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/6026
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.