Multiple processor architecture with flexible external input/output interface
US9792244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Dec 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple processor architecture with flexible external input/output interface is provided. In one embodiment, an open flexible processor architecture avionics device comprises: a multiple processor architecture having a primary processor, a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary and secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.