Flip-flop clustering for integrated circuit design
US9792398B2 · kind B2 · utility
7Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Mar 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system provides placement of components for an integrated circuit having a plurality of flip-flops. The system clusters the plurality of flip-flops into a plurality of clusters and relocates one or more of the flip-flops in response to overlapping placement locations. The clustering includes using a K-means algorithm to assign a flip-flop to a cluster while adding weight to each cluster based on its current size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.