Determination of flip-flop count in physical design
US9792400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method of determining flip-flop counts of interconnects of a physical layout during integrated circuit (IC) design. The outputs of each logic block are defined as primary inputs, and the inputs of each logic block are defined as primary outputs. Each interconnect is traversed from a primary input a primary output to identify the flip-flops and determine the flip-flop count. If an interconnect has a greater flip-flop count than an RTL estimated count, measures are taken to reduce the need for flip-flops with the current routing design. If the interconnect has a smaller flip-flop count than an RTL estimated count, additional flip-flops are inserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.